The influence on over etching and under etching to IC layout is analyzed, the computation model and realization method of IC critical area are presented. 论文在分析过刻蚀和欠刻蚀对IC版图影响的基础上,提出了基于工艺偏差影响的IC关键面积计算新模型和实现方法。
Over etching or under etching in IC process causes the variation of the linewidth and spacing between two parallel lines because of the random disturbance of the process. 在IC的制造过程中,由于工艺的随机扰动,过刻蚀和欠刻蚀造成了导线条的宽度和线间距的变化。
A factor α is defined as the ratio of the current density of the electro-polishing bulk Si over the total current density of the electrochemical etching. 把电抛光体硅的电流密度Je与总的腐蚀电流密度J的比值定义为抛光因子α。